1. Field of the Invention
The present invention relates to a frequency synthesizer based on the phase-locked loop (will be termed PLL hereinafter) scheme.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional frequency synthesizer. In the figure, indicated by 1 is a reference signal oscillator, and 2 is a frequency-dividing phase comparator which compares the phase of a signal derived from the output signal of the frequency synthesizer divided by a factor determined by the input channel data, with the phase of reference signal provided by the reference signal oscillator 1. 3 is a charge pump which generates pulses in accordance with a phase difference signal produced by the dividing phase comparator 2. 4 and 5 are a lag-lead filter and a low-pass filter, respectively, which function to smooth the pulses produced by the charge pump 3.
Indicated by 6 is a first variable-capacitance diode which varies its capacitance in response to the output voltage of the low-pass filter 5, 7 is an oscillator which oscillates at a frequency determined by the capacitance of the first variable-capacitance diode 6, the variable-capacitance diode 6 and oscillator 7 in combination constituting a voltage-controlled oscillator (will be termed VCO hereinafter). 8 is a buffer amplifier for amplifying the output of the oscillator 7, and 9 is an output terminal from which the amplified output of the buffer amplifier 8 is delivered. The output signal of the buffer amplifier 8 is, at the same time, partly fed back to the frequency dividing phase comparator 2.
Next, the operation of the foregoing arrangement will be explained. The output signal fed back from the buffer amplifier 8 is divided by the factor specified by the channel data by the dividing phase comparator 2, and the phase of resulting signal is compared in phase with the phase of the reference signal provided by the reference signal oscillator 1. The phase difference signal resulting from the phase comparison by the phase comparator 2 is fed to the charge pump 3, which then generates pulses in accordance with the received phase difference signal and sends the pulses to the lag-lead filter 4. The pulses generated by the charge pump 3 are smoothed by the lag-lead filter 4 and low-pass filter 5 into a predetermined d.c. voltage, which is applied to the first variable-capacitance diode 6.
The variable-capacitance diode 6 has its capacitance value established in correspondence with the d.c. voltage supplied from the low-pass filter 5, and the oscillator 7 oscillates at a frequency which is determined by the capacitance of the first variable-capacitance diode 6. The output of the oscillator 7 is amplified by the buffer amplifier 8, and the amplified signal is delivered from the output terminal 9 and, at the same time, fed back to the phase comparator 2. The phase-locked loop system operates such that the phase difference as determined by the demultiplying phase comparator 2 ultimately is reduced to zero, and consequently the VCO made up of the variable-capacitance diode 6 and oscillator 7 has its oscillation frequency stabilized at to a certain value. This state of operation is called "a locked state".
The conventional frequency synthesizer, arranged as described above, needs a substantial amount of time for frequency matching in the phase lock process, which is dependent on the time constant of the lag-lead filter 4. Therefore it cannot achieve a quick variation of the voltage applied to the first variable-capacitance diode 6 at the switching of frequencies, resulting adversely in an excessive time delay for channel switching, and it exhibits a problem of being deficient as a frequency synthesizer used in digital radio communications equipment in which frequency "hopping" is required.
An example of a scheme which copes with this problem is described in Japanese Patent Unexamined Publication No. 57-160227, however, it still involves a problem of prolonged switching time due to the temperature fluctuation of the VCO.